1. Field of the Invention
The present invention relates to a switching power supply device and an image forming apparatus in which this power supply device is mounted.
2. Description of the Related Art
As an example of the switching power supply devices of the conventional synchronous rectification type, a circuit configuration is well known, which uses a comparator as illustrated in FIG. 10. In FIG. 10, this circuit includes a transformer 1001, a DC power supply, a primary side MOSFET 1003, a secondary side electrolytic capacitor 1004, a load 1005, a switching control circuit 1006, a synchronous rectification FET 1007 (hereafter referred to as an FET 1007), and a comparator 1008. After the MOSFET 1003 (hereafter referred to as an FET 1003) turns on to store energy in the transformer 1001, when the FET 1003 turns off, the voltage at the source terminal of the FET 1007 rises, so that the voltage of the plus terminal of the comparator 1008 becomes higher than the voltage of the minus terminal, and the FET 1007 turns on. A current flows through the FET 1007 and decreases to 0 A (0 ampere). When a current starts to flow from the plus terminal of the capacitor 1004 to the transformer 1001, the voltage at the minus input terminal of the FET 1007 becomes higher than the voltage at the plus input terminal, and the voltage at the gate terminal of the FET 1007 drops to turn the FET 1007 off. In the configuration described above, it becomes possible to control the on/off of the synchronous rectification FET 1007 by using a fewer component parts. Another synchronous rectification circuit can be configured by replacing the comparator in FIG. 10 with a circuit consisting of a PNP transistor and an NPN transistor, and by using a PNP transistor instead of the currently used MOSFET for the synchronous rectification switching element.
The circuit in FIG. 10 is based on a system of directly detecting a current flowing in the transformer. In contrast, as a way of not directly detecting a current, there is a method which utilizes an ET product of a transformer described in Japanese Patent No. 4126558 (a product of a pulse voltage by a pulse width of a pulse waveform that can pass through a transformer). FIG. 10 is a circuit diagram disclosed in Japanese Patent No. 4126558. In FIG. 10B, the circuit includes a transformer 1201, a power supply 1202, a primary side FET 1203, a synchronous rectification FET 1204, a secondary side electrolytic capacitor 1205, a load 1206, a first constant current supply 1207, a capacitor 1208, a second constant current supply 1209, a reference voltage 1210, a comparator 1211, and resistances 1212 and 1213. The constant current supply 1207 generates a current proportional to a voltage generated in the transformer 1201 for a period when the primary side FET 1203 is ON, and stores, as a voltage of the capacitor, an integrated value of voltage that appears in the transformer for a period when the FET 1203 is ON. The second constant current supply 1209 generates a current proportional to a voltage that appears for a period when the FET 1203 is off, and when the FET 1203 turns off, a switch 1217 turns on to discharge the voltage stored in the capacitor 1208. When the voltage of the capacitor 1208 drops to a predetermined value which is determined by a reference voltage 1210, the comparator 1211 operates to invert a logic circuit to turn off the synchronous rectification FET 1204.
To cite other examples, as discussed in Japanese Patent Application Laid-Open Nos. 2005-151780 and 2005-143287, there are a system in which a reference voltage supply is provided in series with an input terminal of the comparator, and another system in which a plurality of reference voltages serving as thresholds are provided to realize a hysteresis property to prevent malfunctioning of the circuit.
In a conventional configuration illustrated in FIG. 10, however, since the synchronous rectification FET has a small resistance between the drain and source when it is in the ON state. Therefore, if the drain-source voltage of the synchronous rectification FET is low, the FET is unable to operate correctly. Particularly when the secondary side synchronous rectification FET is operated under light load in power supply critical mode or in discontinuous mode, the current that flows in the FET decreases to almost 0 A. Therefore, the drain-source voltage of the synchronous rectification FET falls, making the FET unable to accomplish an OFF-to-ON transition correctly.
The above situation can be solved by using an FET with a high drain-source resistance for the synchronous rectification FET. However, in the FET with a high drain-source resistance, its efficiency decreases during a synchronous rectification. As it is expected that the drain-source resistance of the FET itself as a switch tends to decrease more and more, this situation may become more obvious in the future.
In Japanese Patent No. 4126558, since the current flowing in the transformer is not detected directly, the performance is not influenced by the drain-source resistance of the synchronous rectification FET. Since this power supply device uses an integrator, the circuit is less likely to malfunction and the circuit configuration is simple. However, a threshold value is to be adjusted so that OFF timing of the synchronous rectification FET is set to go with 0 A current. The adjustment of the threshold value is not easy. The reason is as follows. If an output voltage changes or load changes when power supply is turned on, an average value as a center value in charging or discharging of the capacitor changes, so that timing of a current becoming 0 A does not agree with turning off of the synchronous rectification FET. In other words, because the current is not detected directly, an estimation operation is performed, and the FET is to be turned off early to secure some time margin. This prolongs the conduction time of a body diode in the synchronous rectification FET and reduces the efficiency of operation.